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M66281FP
5120 x 8-Bit x 2 Line Memory
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Description
The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words x 8 bits x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the compensation of data of multiple lines.
Features
* * * * * * * * * * Memory configuration: 5120 words x 8 bits x 2 (dynamic memory) High speed cycle: 25 ns (Min) High speed access: 18 ns (Max) Output hold: 3 ns (Min) Reading and writing operations can be completely carried out independently and asynchronously Variable length delay bit Input/output: TTL direct connection allowable Output: 3 states Q00 to Q07: 1 line delay Q10 to Q17: 2 line delay
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs D0 to D7
31 30 29 28 27 23 22 21
Data outputs Q0 to Q7
45 46 47 2 3 4 5
6
Data outputs Q10 to Q17
9 10 11 12 13 16 17 18
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
WEB 36 Write enable input WRESB 35 Write reset input WCK 34 Write clock input VCC
42 REB
Read enable input
(
Memory array 5120 words x 8 bits x 2 Memory only for 1 line delay data Memory only for 2 line delay data
41 RRESB Read reset input
40 RCK
Read clock input
)
8
7 GND
20 GND
33 GND
43 GND
VCC 19 VCC 32
VCC 44
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 1 of 15
M66281FP
Pin Arrangement
36 WEB 35 WRESB 34 WCK 33 GND
32 VCC 31 D0
26 NC 25 NC
24 NC 23 D5 22 D6 21 D7 20 GND 19 VCC 18 Q17 17 Q16 16 Q15 15 NC
38 NC 37 NC
NC RCK RRESB REB GND VCC Q00 Q01 Q02 NC
39 40 41 42 43 44 45 46 47 48
M66281FP
10
28 D3 27 D4 11 12
30 D1 29 D2
NC Q03 Q04 Q05 Q06 Q07 GND VCC Q10 Q11 Q12 Q13 Q14 NC
14
13
1
2
3
4
5
6
7
8
9
(Top view) Outline: PRQP0048JA-A (48P6S-A)
NC: No connection
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 2 of 15
M66281FP
Absolute Maximum Ratings
(Ta = 0 to 70C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Note: * Symbol VCC VI VO Pd Tstg Ratings -0.3 to +4.6 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 540 -55 to 150 Unit V V V mW C * Conditions Value based on the GND pin
Ta = 0 to 63C. Ta > 63C are derated at -9 mW / C
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating temperature Symbol VCC GND Topr Min 2.7 0 Typ 3.15 0 Max 3.6 70 Unit V V C
Electrical Characteristics
(Ta = 0 to 70C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Symbol VIH VIL VOH VOL IIH Min 2.0 VCC - 0.4 Typ Max 0.8 0.4 1.0 Unit V V V V A IOH = -4 mA IOL = 4 mA VI = VCC WEB, WRESB, WCK, REB, RRESB, RCK, D0 to D7 WEB, WRESB, WCK, REB, RRESB, RCK, D0 to D7 Test Conditions
Low-level input current
IIL
-1.0
A
VI = GND
Off-state high-level output current Off-state low-level output current Average supply current during operation Input capacitance Off-time output capacitance
IOZH IOZL ICC CI CO

5.0 -5.0 150 10 15
A A mA pF pF
VO = VCC VO = GND VI = VCC, GND, Output open tWCK, tRCK = 25 ns f = 1 MHz f = 1 MHz
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 3 of 15
M66281FP
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are written into memory only for 1 line delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter of memory only for 1 line delay data is incremented simultaneously. When WEB is set to "H", the writing operation is inhibited and the write address counter of memory only for 1 line delay data stops. When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is initialized. When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to data outputs Q00 to Q07 and the contents of memory only for 2 line delay data are output to Q10 to Q17 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counters of memory only for 1 line delay data and memory only for 2 line delay data are incremented simultaneously. In addition, data of Q00 to Q07 is written into memory only for 2 line delay data in synchronization with a rising edge of RCK. When this is the case, the write address counter of memory only for 2 line delay data is then incremented. When REB is set to "H", operation for reading data from memory only for 1 line delay and from memory only for 2 line delay data is inhibited and the read address counter of each memory stops. Outputs Q00 to Q07 and Q10 to Q17 are placed in a high impedance state. In addition, the write address counter of memory only for 2 line delay data then stops. When read reset input RRESB is set to "L", the read address counters of memory only for 1 line delay data as well as the write address counter and read address counter of memory only for 2 line delay data are then initialized.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 4 of 15
M66281FP
Switching Characteristics
(Ta = 0 to 70C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item Access time Output hold time Output enable time Output disable time Symbol tAC tOH tOEN tODIS Min 3 3 3 Typ Max 18 18 18 Unit ns ns ns ns
Timing Requirements
(Ta = 0 to 70C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time for WCK Input data hold time for WCK Reset setup time for WCK/RCK Reset hold time for WCK/RCK Reset non-selection setup time for WCK/RCK Reset non-selection hold time for WCK/RCK WEB setup time for WCK WEB hold time for WCK WEB non-selection setup time for WCK WEB non-selection hold time for WCK REB setup time for RCK REB hold time for RCK REB non-selection setup time for RCK REB non-selection hold time for RCK Input pulse up/down time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Min 25 11 11 25 11 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Typ Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Notes: Perform reset operation after turning on power supply. * For 1 line access, the following conditions must be satisfied: WEB high-level period 20 ms - 5120 * tWCK - WRESB low-level period REB high-level period 20 ms - 5120 * tRCK - RRESB low-level period
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 5 of 15
M66281FP
Switching Characteristics Measurement Circuit
VCC RL = 1 k Qn SW1 CL = 30 pF: tAC, tOH Qn SW2 CL = 5 pF: tOEN, tODIS RL = 1 k
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns Judging voltage Input: 1.3 V
Output: 1.3 V (However, tODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is judged with 90% of the output amplitude) Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) SW1 Close Open Close Open SW2 Open Close Open Close
tODIS and tOEN Measurement Condition
3V RCK 1.3 V 1.3 V GND
3V REB GND tODIS (HZ) 90% Qn tODIS (LZ) Qn 10% 1.3 V tOEN (ZL) tOEN (ZH) VOH
1.3 V
VOL
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 6 of 15
M66281FP
Operation Timing
Write Cycle
n cycle n + 1 cycle n + 2 cycle Disable cycle n + 3 cycle n + 4 cycle
WCK
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WEB
tDS tDH
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
WRESB = "H"
Write Reset Cycle
n - 1 cycle n cycle Reset cycle 0 cycle 1 cycle 2 cycle
WCK
tWCK tNRESH tRESS tRESH tNRESS
WRESB
tDS tDH
Dn
(n - 1)
(n)
(0)
(1)
(2)
WEB = "L"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 7 of 15
M66281FP Matters that Needs Attention when WCK Stops
n cycle n + 1 cycle n cycle Disable cycle
WCK
tWCK tNWES
WEB
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n) into memory
Period for writing data (n) into memory WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 8 of 15
M66281FP Read Cycle
n cycle n + 1 cycle n + 2 cycle Disable cycle n + 3 cycle n + 4 cycle
RCK
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
REB
tODIS
tAC
tOEN
Q0n (Q1n)
(n)
(n + 1)
(n + 2)
HIGH-Z
(n + 3) tOH
(n + 4)
RRESB = "H"
Read Reset Cycle
n - 1 cycle n cycle Reset cycle 0 cycle 1 cycle 2 cycle
RCK
tRCK tNRESH tRESS tRESH tNRESS
RRESB
tAC
Q0n (Q1n)
(n - 1)
(n)
(0)
(0)
(0) tOH
(1)
(2)
REB = "L"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 9 of 15
M66281FP Notes on Reading of Written Data in Read Disable When writing operation is performed at n cycle and n + 1 cycle on the writing side in the read disable period after n - 1 cycle on the reading side, output at n cycle and n + 1 cycle after read enable is invalid. For output at n + 2 cycle and after, however, data written in the read disable period is to be output.
n - 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle n + 4 cycle n + 5 cycle n + 6 cycle n + 7 cycle
WCK
tDS tDH
Dn
(n - 1)
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
(n + 5)
(n + 6)
(n + 7)
n - 1 cycle
Disable cycle
n cycle
n + 1 cycle n + 2 cycle
RCK
REB
tAC
tODIS (n - 1) HIGH-Z
tOEN
Q0n (Q1n)
Invalid
Invalid
(n + 2)
WEB = "L" WRESB = "H" RRESB = "H"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 10 of 15
M66281FP
Variable Length Delay Bit
1 Line (5120 Bits) Delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay.
5120 cycle 5121 cycle 5122 cycle (0') (1') (2')
0 cycle
1 cycle
2 cycle
5118 cycle 5119 cycle
WCK RCK
tRESS tRESH
WRESB RRESB
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
5120 cycle
tAC
tOH
Q0n (Q1n)
(0)
(1)
(2)
(3)
WEB, REB = "L"
n-bit Delay Bit (Reset at cycles according to the delay length)
n - 2 cycle n - 1 cycle n cycle (0') n + 1 cycle n + 2 cycle n + 3 cycle (1') (2') (3')
0 cycle
1 cycle
2 cycle
WCK RCK
tRESS tRESH tRESS tRESH
WRESB RRESB
tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n - 3)
(n - 2)
(n - 1)
(0')
(1')
(2')
(3')
m cycle
tAC
tOH
Q0n (Q1n)
(0)
(1)
(2)
(3)
WEB, REB = "L" m3
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 11 of 15
M66281FP n-bit Delay 2 (Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle 1 cycle 2 cycle n - 2 cycle n - 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle
WCK RCK
tRESS tRESH
WRESB
tRESS tRESH
RRESB
tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n - 2)
(n - 1)
(n)
(n + 1)
(n + 2)
(n + 3)
m cycle
tAC
tOH
Q0n (Q1n)
(0)
(1)
(2)
(3)
WEB, REB = "L" m3
n-bit Delay 3 (Slides address by disabling REB in the period according to the delay length)
0 cycle 1 cycle 2 cycle n - 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle
WCK RCK
tRESS tRESH
WRESB RRESB
tNREH tRES
REB
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(n - 2)
(n - 1)
(n)
(n + 1)
(n + 2)
(n + 3)
m cycle
tAC
tOH
Q0n (Q1n)
HIGH-Z
Invalid (1)
(2)
(3)
WEB = "L" m3
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 12 of 15
M66281FP Reading Shortest n-cycle Write Data "n" (Reading side n - 2 cycle ends after the end of writing side n + 1 cycle) When the reading side n - 2 cycle ends before the end of the writing side n + 1 cycle, output Qn of n cycle is made invalid. In the following diagram, end of reading side n - 2 cycle and end of writing side n + 1 cycle overlap each other. This example can read n cycle data in the shortest time. When this is the case, reading operation at n - 1 cycle is invalid.
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
WCK
Dn
(n)
(n +1)
(n + 2)
(n + 3)
n - 2 cycle
n - 1 cycle
n cycle
RCK
Q0n (Q1n)
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay (When writing side n-cycle <2> starts, reading side n cycle <1> then starts) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n - 1) <1>*
(n) <1>*
(0) <2>*
(n - 1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Q0n (Q1n)
(n - 1) <0>*
(n) <0>*
(0) <1>*
(n - 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 13 of 15
M66281FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
N n line image data
M66281 D0 Q00 to to D7 Q07 1 line delay
B (n + 1) line image data
x2
Adder N + K {2N - (A + B) }
Compensated image data
Subtractor 2N - (A + B)
xK
2 line delay
Sub scan direction
Main scan direction
A N B
(n - 1) line n line (n + 1) line N' = N + K { (N - A) + (N - B) } = N + K {2N - (A + B)} K: Laplacian coefficient
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 14 of 15
Adder A+B
Q10 to Q17
A (n - 1) line image data
M66281FP
Package Dimensions
JEITA Package Code P-QFP48-7x10-0.65 RENESAS Code PRQP0048JA-A Previous Code 48P6S-A MASS[Typ.] 0.3g
HD
*2 38
D
25
39
24
*1
HE
E
48
15
Reference Symbol
ZE
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
Dimension in Millimeters
1
ZD
Index mark
14
c
F
D E A2 HD HE A A1 bp c
L Detail F
x
REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page 15 of 15
A1
e
y
*3
bp
e x y ZD ZE L
Nom Max 10.0 10.2 7.0 7.2 1.85 11.7 12.0 12.3 8.7 9.0 9.3 2.15 0 0.1 0.2 0.2 0.25 0.35 0.13 0.15 0.2 0 10 0.65 0.13 0.10 0.775 0.575 0.3 0.5 0.7
Min 9.8 6.8
A
A2
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